Silicon Labs /Series1 /EFM32GG12B /EFM32GG12B410F1024IL112 /SDIO /CTRL

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Interpret as CTRL

31282724232019161512118743000000000000000000000000000000000000000000 (ITAPDLYEN)ITAPDLYEN0ITAPDLYSEL0 (ITAPCHGWIN)ITAPCHGWIN0 (OTAPDLYEN)OTAPDLYEN0OTAPDLYSEL0TXDLYMUXSEL

Description

Core Control Signals

Fields

ITAPDLYEN

Selective Tap Delay Line Enable on Rxclk_in

ITAPDLYSEL

Selects One of 32 Taps on the Rxclk_in Line

ITAPCHGWIN

Gating Signal for Tap Delay Change

OTAPDLYEN

Selective Tap Delay Line Enable on SDIO_CLK Pin

OTAPDLYSEL

Selects One of 32 Taps on the SDIO_CLK Pin

TXDLYMUXSEL

TX Delay Mux Selection

Links

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